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DATA SHEET
Part No. Package Code No.
AN12978A
UBGA015-W-2020
Publication date: October 2008
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AN12978A Contents
Overview Features Package Type ........................................................................................................................... 3 ........................................................................................................................... 3 ...................................................................................................................... 3 ............................................................................................................................ 3
Applications
............................................................................................................................... 3 .................................................................................................................. 5 .................................................................................................... 6 ...................................................................................................... 7 ............................................................. 9
Application Circuit Example (Block Diagram) ............................................................................. 4 Pin Descriptions Absolute Maximum Ratings Electrical Characteristics Technical Data Usage Notes
Operating Supply Voltage Range ............................................................................................. 6 Electrical Characteristics (Reference values for design)
.................................................................................................................. 10 ...................................................................................................................... 20
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AN12978A
AN12978A
Monaural BTL amplifier IC with built-in AGC (I2C bus-control correspondence)
Overview AN12978A is the monaural BTL amplifier which contained the AGC circuit for clip prevention of a speaker output. This IC performs a mode change by the I2C bus control system. (Standby function ON/OFF change etc.) Features Selection by I2C bus control is possible in the on-level of AGC. (3-bit, 8-step) Selection by I2C bus control is possible in an attack/recovery time of AGC. (attack: 2-bit , recovery: 3-bit) The resistance and the capacitor of a detector circuit which were being used for the conventional AGC are unnecessary. In order to realize high efficiency of output power, it adopts CMOS power amplifier circuit. Built-in shutdown function. Built-in Gv-Switch. Applications Audio amplifier for mobile, such as a cellular phone Package
15 pin Wafer level chip size package (WLCSP) Size: 2.0 mm x 2.0 mm (0.5 mm pitch)
Type
Bi-CMOS IC
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AN12978A
Application Circuit Example (Block Diagram)
VCC = 3 V Speaker 8 Shutdown Operate 1 F 1 F OUT_NEG 11 +14 dB GNDSP 12 7 OUT_POS 13 +14dB 2.2 k SDA 1 F VCCD = 1.8 V VREFSP 10 9 8 SD
VCCD
VCCSP = 3 V 1 F
DET 14 AGC +3 dB/+6 dB GND 15
I2C-BUS Control
6
5 SCL
2.2 k
1 VREF 1 F
2 PREOUT
3 100 pF FB
4 GND
10 k 0.1 F
10 k
INPUT
Note)
1. This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set. 2. The threshold voltage at 8pin has the VCCD dependency.
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AN12978A
Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin name VREF PREOUT FB GND SCL SDA VCCD SD VCC VREFSP OUT_NEG GNDSP OUT_POS VCCSP GND Type Output Output Input Ground Input Input / Output Power Supply Input Power Supply Output Output Ground Output Power Supply Ground Reference Voltage Output Pre-amplifier Output Pre-amplifier Negative Feedback Input Ground SCL Input on I2C-bus Control SDA Input on I2C-bus Control Power supply for logic circuit Shutdown Control Power supply Reference Voltage Output for Speaker Amplifier Speaker Output (Negative Phase) Ground for Speaker Amplifier Speaker Output (Positive Phase) Power supply for Speaker Amplifier Ground Description
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AN12978A
Absolute Maximum Ratings
A No. Parameter Symbol VCC 1 Supply voltage VCCD VCCSP 2 3 4 5 Supply current Power dissipation Operating ambient temperature Storage temperature ICC PD Topr Tstg Rating 5.5 3.6 5.5 -- 120 -20 to +70 -55 to +150 A mW C C *2 *3 *3 V *1 Unit Note
Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 70C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the * PD - Ta diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25C.
Operating Supply Voltage Range
Parameter Symbol VCC Supply voltage range VCCD VCCSP Range 2.7 to 4.5 1.7 to 2.6 1.7 to 3.3 2.7 to 4.5 V *1 *2 Unit Note
Note) 1. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. 2. *1: The values under Fast mode. *2: The values under Standard mode.
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AN12978A
Electrical Characteristics at VCC = 3.0 V , VCCD = 1.8 V , VCCSP = 3.0 V
Note) Ta = 25C2C unless otherwise specified.
B No. Circuit Current 1 2 3 4 5 6 7 8 9
Parameter
Symbol
Conditions
Limits Min Typ Max
Unit
No te
Circuit current at non-signal 1 (VCC) Circuit current at non-signal 2 (VCCSP) Circuit current at non-signal 3 (VCCD) Circuit current at standby mode 1 (VCC) Circuit current at standby mode 2 (VCCSP) Circuit current at standby mode 3 (VCCD) Circuit current at speaker save mode 1 (VCC) Circuit current at speaker save mode 2 (VCCSP) Circuit current at speaker save mode 3 (VCCD)
IVCC1A IVCC2A IVCC3A IVCC1B IVCC2B IVCC3B IVCC1C IVCC2C IVCC3C
VCC = 3.0V, Non-signal STB = OFF, SP = ON, AGC = ON VCCSP = 3.0V, Non-signal STB = OFF, SP = ON, AGC = ON VCCD = 1.8V, Non-signal STB = OFF, SP = ON, AGC = ON VCC = 3.0V, Non-signal STB = ON, SP = OFF, AGC = ON VCCSP = 3.0V, Non-signal STB = ON, SP = OFF, AGC = ON VCCD = 1.8V, Non-signal STB = ON, SP = OFF, AGC = ON VCC = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ON VCCSP = 3.0 V, Non-signal STB = OFF, SP = OFF, AGC = ON VCCD = 1.8 V, Non-signal STB = OFF, SP = OFF, AGC = ON
0.5 1.0 0.5
2.4 6.5 0.1 0.1 0.1 0.1 2.4 0.3 0.1
4.5 15.5 10 1.0 1.0 1.0 4.5 1.0 10
mA mA A A A A mA mA A
Input/output characteristics 11 SP reference output level VSPO Vin = -31.0 dBV , f = 1 kHz RL = 8 , GAIN = +23 dB Vin = -31.0 dBV, f = 1 kHz RL = 8 , GAIN = +23dB to THD5th Non-Signal using A curve filter GAIN = +23 Db THD = 10%, f = 1 kHz RL = 8, AGC = OFF Vin = -31.0 dBV, f = 1 kHz RL = 8 , GAIN = +23 dB using A curve filter -9.5 -8.0 -6.5 dBV
12 SP reference output distortion
THSPO
0.07
0.5
%
13 SP output noise voltage
VNSPO
300
-78
-71 -90
dBV
14 SP maximum rating output 15 SP output level at power save
VMSPO VSSPO
500 -114
mW dBV
16 SP AGC output level 1
Vin = -17.0 dBV, f = 1 kHz VSPOA1 RL = 8 , GAIN = +23 dB AGC-Level = 4 dBV Vin = -12.0 dBV, f = 1 kHz VSPOA2 RL = 8 , GAIN = +23 dB AGC-Level = 4 dBV
3.0
4.0
5.0
dBV
17 SP AGC output level 2
3.0
4.0
5.0
dBV
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AN12978A
Electrical Characteristics at VCC = 3.0 V , VCCD = 1.8 V , VCCSP = 3.0 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No. I2C interface
Parameter
Symbol
Conditions
Limits Min Typ Max 0.3 x VCCD VCCD + 0.5 0.2 x VCCD 10 400
Unit
No te
43 SCL, SDA signal input Low Level 44 SCL, SDA signal input Low Level 45 SDA output signal Low Level 46 SCL,SDA Signal Input Current 47 SCL maximum frequency of signal input
VIL VIH VOL Ii fSCL

Open corrector Sync current: 3 mA Input voltage: 0.1 V to 1.7 V
- 0.5 0.7 x VCCD 0 -10 0

V V V A kHz
The threshold voltage at 8-pin 48 SD input Low Level 49 SD input High Level Vresetlth Vresethth 0.9 x VCCD 0.1 x VCCD V V
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AN12978A
Electrical Characteristics (Reference values for design) at VCC = 3.0 V , VCCD = 1.8 V , VCCSP = 3.0 V
Note) Ta = 25C2C unless otherwise specified. The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, we will respond in good faith to user concerns.
B No. I2C interface 66 67 68 69 70 71 72 73 74 75
Parameter
Symbol
Conditions
Limits Min Typ Max
Unit
No te
Bass free time between a condition of stop and a condition of start Setup time of a condition of start Hold time of a condition for start "L" time of SCL clock "H" time of SCL clock Rising time of SDA, SCL signal Fall time of SDA,SCL signal Data setup time Data hold time Rising up time of a condition of stop
tBUF tSU;STA tHD;STA tLow tHigh tR tF tSU;DAT tHD;DAT tSU;STO

1.3 0.6 0.6 1.3 0.6 0.1 0 0.6

0.3 0.3 0.9
s s s s s s s s s s
*1 *1 *1 *1 *1 *1 *1 *1 *1 *1
Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard. *2: VIHmin is the minimum limit of the signal input high level. *3: VILmax is the maximum limit of the signal input low level. Repeated START CONDITION
VIHmin (*2) VILmax (*3)
START CONDITION
STOP CONDITION
START CONDITION
SDA tF tLow tR tSU;DAT tF
tBUF tR
tHD;STA
SCL tHD;STA tHD;DAT tHigh tSU;STA tSU;STO
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AN12978A
Technical Data
I2C-bus Mode 1. Write Mode
SDA
SCL SLAVE ADDRESS SUB ADDRESS DATA ACK ACK STOP CONDITION
START CONDITION
ACK
1011 B
0110 6
0000
0001
1000 8
0000 0
0 1 Example of transmission messages
Two transmission messages (i.e., the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following description provides information on the structure of the frame.
When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver will be enabled. When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver will be aborted. The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be aborted. _{The sub address is a specified one unique to each function. Data is information under control. The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level signal returned from the receiver as shown by the dotted lines in Fig. The communication will be aborted if the low signal is not returned. The SDA will not change when the level of the SCL is high except start or stop conditions are enabled.
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AN12978A
Technical Data (continued)
I2C-bus Mode (continued) 1. Write Mode (continued) (a) I2C-bus PROTOCOL Slave address: 10110110 (B6Hex) Format (normal)
S Start condition Slave address WA Sub address A Data byte A P Stop condition
Acknowledge bit Write Mode: 0
(b) Auto increment Sub-address 0*Hex: Auto increment mode (When the data is sent in sequence, the sub address will change one by one and the data will be input.) Auto increment mode
S Slave address WA Sub address A Data 1 A Data 2 A Data n A P
(c) Initial condition The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0 (Note.1) will be absolutely 0, when the power is turned ON. (d) Sub-address Byte and Data Byte Format Sub-address
MSB
Data byte D6 D5 D4 D3 AGC 0 OFF 1 ON D2 SP Save 0 ON 1 OFF D1 Standby 0 ON 1 OFF
LSB
D7
D0
*0Hex
AGC-ON GAIN VCCSP 0 +23dB dependence 1 +26dB 0 OFF 1 ON AGC-ON data bit3 0 (Note.2) AGC-ON data bit2 0 (Note.2)
0 (Note.2)
0 (Note.2)
0 (Note.1)
*1Hex
AGC-ON AGC-REC AGC-REC AGC-REC AGC-ATT AGC-ATT data bit1 data bit3 data bit2 data bit1 data bit2 data bit1 0 (Note.2) 0 (Note.2) 0 (Note.2) 0 (Note.2)
*2Hex
<00Hex Register> D0, D4, D5: Always set to 0 0 D1: Standby ON/OFF switch (Note.2) D2: SP Save ON/OFF switch D3: AGC ON/OFF switch D6: AGC-ON VCCSP dependence ON/OFF selection D7: GAIN +17 dB/+20 dB selection <01Hex Register> D0, D1 : AGC-attack-time selection D2, D3,D4: AGC-recovery-time selection D5,D6,D7: AGC-on-level selection <02Hex Register> D0 to D7: Always set to 0 (test & adjust mode)
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Please use these bit only Data = "0", because they are used by our company's final test and fine-tuning AGC-on level.
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AN12978A
Technical Data (continued)
I2C-bus Mode (continued) 1. Write Mode (continued) (e) AGC-attack-time selection Write 01Hex Register D1 0 0 1 1 D0 0 1 0 1 Attack time 0.5 ms 1 ms 2 ms 4 ms (f) AGC-recovery-time selection Write 01Hex Register D4 0 0 0 0 1 1 1 1 (g) AGC-on-level selection (at VCC = 3.0 V, VCCSP = 3.0 V) Write 01Hex Register D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 AGC On Level 1 dBV 2 dBV 3 dBV 4 dBV 5 dBV 6 dBV 7 dBV 8 dBV Output Po ( RL = 8W ) 157 mW 198 mW 249 mW 314 mW 395 mW 498 mW 626 mW 789 mW VCCSP () -- -- -- 3.0 V 3.3 V 3.7 V 4.1 V 4.5 V D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Recovery time 1.0 s 1.5 s 2.0 s 3.0 s 4.0 s 6.0 s 8.0 s 12.0 s
(h) AGC-on-level VCCSP dependence mode (at AGC On Level = 4 dBV) AGC ON level increases by 0.75 dBV with each 0.3 V increase of VCCSP, and baseline of VCCSP is 3.0 V at AGC-onlevel VCCSP dependence mode. When VCCSP is 3.0 V, AGC ON level is set according to table (g). VCCSP 2.7 V 3.0 V 3.3 V 3.6 V AGC On Level 3.25 dBV 4 dBV 4.75 dBV 5.5 dBV Output Po ( RL = 8 ) 264 mW 314 mW 373 mW 444 mW VCCSP 3.9 V 4.2 V 4.5 V AGC On Level 6.25 dBV 7 dBV 7.75 dBV Output Po ( RL = 8 ) 527 mW 626 mW 745 mW
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AN12978A
Technical Data (continued)
I2C-bus Mode (continued) 2. Read Mode (a) I2C-bus PROTOCOL Slave address 10110111(B7Hex) Format
S Slave address R A Data 0 A Data 1 A Data 2 A P
Read Mode: 1 Note) At the slave address input, it is sequentially output from data 0. There is no necessity for inputting the sub-address.
(b) Sub-address Byte and Data Byte Format
MSB
Data byte D6 D5 D4 D3 D2 D1
LSB
D7
D0
Data 0
Sub address Sub address Sub address Sub address Sub address Sub address Sub address Sub address *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex *0Hex Latch data Latch data Latch data Latch data Latch data Latch data Latch data Latch data [D0] [D1] [D2] [D3] [D4] [D5] [D6] [D7] Sub address Sub address Sub address Sub address Sub address Sub address Sub address Sub address *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex *1Hex Latch data Latch data Latch data Latch data Latch data Latch data Latch data Latch data [D0] [D1] [D2] [D3] [D4] [D5] [D6] [D7] Sub address Sub address Sub address Sub address Sub address Sub address Sub address Sub address *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex *2Hex Latch data Latch data Latch data Latch data Latch data Latch data Latch data Latch data [D2] [D3] [D4] [D5] [D6] [D7] [D1] [D0]
Data 1
Data 2
Operating temperature guarantee of I2C-bus Control
The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25C) by inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control. But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection. If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns.
Usage note of I2C bus
The I2C bus of this product is designed to correspond to Standard mode (100 Kbps) and Fast mode (400 Kbps) in Philips Corporation I2C specification version 2.1. However, not correspond to High Speed mode (to 3.4 Mbps). This product operate as a slave device in I2C bus system. This product is not confirm to operate in multi-master bus system and mixing -speed bus system. And this product is not confirm connectivity to CBUS receiver. If using this product in these mode, please confirm availability to our company. Purchase of Panasonic I2C components conveys a license to use these components in an I2C systems under the Philips I2C patent right on condition that using condition conform to I2C standard specification approved by Philips Corporation.
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AN12978A
Technical Data (continued)
I/O block circuit diagrams and pin function descriptions
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Waveform and voltage
VCC
Internal circuit
Description
VREF 1 DC 1.45 V
10k 1k 150k
Reference Voltage Output
150k
VCC
PREOUT 2 DC 1.45 V
500
Pre-amplifier Output
FB 3 DC 1.45 V
10k
Pre-amplifier Negative Feedback Input
4
GND
Ground
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AN12978A
Technical Data (continued)
I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Waveform and voltage
Internal circuit
VCCD
Description
SCL 5 Hi-Z SCL Input on I2C-Bus Control
VCCD
SDA 6 Hi-Z SDA Input on I2C-Bus Control
GND
VCCD 7 1.8 V(typ.)
Power Supply for Logic Circuit
VCCD
SD 8 Connect VCCD to VCC 1.8 V to 3.0 V
Shutdown Control Shutdown mode is shorted to GND. (All data becomes 0.)
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AN12978A
Technical Data (continued)
I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Waveform and voltage
Internal circuit
Description
VCC 9 3.0 V(typ.) Power Supply
VCC
VREFSP 10 3.0 V(typ.)
10k 1k 150k
Reference Voltage Output for Speaker Amplifier
150k
VCCSP
OUT_NEG 11 DC 1.45 V
400k GNDSP
Speaker Output (Negative Phase)
12
GNDSP
--
Ground for Speaker Amplifier
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AN12978A
Technical Data (continued)
I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin No.
Waveform and voltage
Internal circuit
VCCSP
Description
OUT_POS 13 DC 1.45 V
400k GNDSP
Speaker Output (Positive Phase)
VCCSP 14 3.0 V(typ.)
Power Supply for Speaker Amplifier
15
GND
Ground
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AN12978A
Technical Data (continued)
Power supply and logic sequence
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop performance caused in switching. 1. The sequence of the power supply and each logic
Please first bring up the power supply, and then the standby off.
The basic procedure at the power-on
1. The power OFF condition Both the standby and the SP_Save are in the ON condition. 2. Power ON 3. Standby Off 4. SP_Save Off
VCC,VCCSP, VCCD Power supply Off
On
On Off
Off Standby On Off SP_Save On 20 ms or more * Off
Off On
The basic procedure at the power-off
1. The power ON condition Both the standby and the SP_Save are in the OFF condition. 2. SP_Save On ( = Standby On) 3. Standby On 4. Power Off
On 0 ms or more
After at least 20 ms has passed after the standby off, please off SP_Save.
Please control Standby On to simultaneous with SP_Save On, or the back.
Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off. It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and resistance linked to an input terminal (IN). It is a recommendation value in a constant given in the example of Application Circuit Example (Block Diagram).
2The sequence of VCC and VCCSP and VCCD This IC have not a standup and falling order in VCC and VCCSP. A standup and falling time of VCC and VCCSP recommend 1 or more ms.
VCC VCCSP VCCD
On Off
On Off
1 ms or more
1 ms or more
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AN12978A
Technical Data (continued)
PD Ta diagram
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AN12978A
Usage Notes
1. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as SP output pin (Pin11, Pin13) - power supply pin short, SP output pin (Pin11, Pin13) - GND short, or SP output (Pin11, Pin13) -to-SP output-pin short (load short). 2. Please absolutely do not mount the IC in the reverse direction on to the printed-circuit-board. It damaged when the electricity is turned on. 3. Please do not make it open, because the open SD-pin (Pin8) is not fixed.
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Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: - Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. - Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20080805}

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